1. Field of the Invention
The present invention relates to a MOS transistor and a method for forming the MOS transistor, and more particularly, to a MOS transistor in which a gate poly oxide layer is formed to a predetermined thickness on a semiconductor substrate and a method for forming the MOS transistor
2. Description of the Related Art
As the integration density and storage capacity of semiconductor devices increase, the size of MOS transistors continues to decrease. Accordingly, the thicknesses of a gate oxide layer and a gate poly oxide layer and the depth of a junction region, such as a source/drain region, decrease.
FIGS. 1 through 4 are cross-sectional views illustrating a conventional method for manufacturing a MOS transistor. Referring to FIG. 1, a gate oxide layer pattern 30 and a gate conductive layer pattern 35 are sequentially formed on a semiconductor substrate 10 in which a shallow trench isolation (STI) 20 is formed.
Next, as shown in FIG. 2, a gate poly oxide layer 40 is formed over the entire surface of the semiconductor substrate 10, and a source/drain region 45 is formed on the semiconductor substrate 10. As the size of a MOS transistor decreases, the thickness of the gate poly oxide layer 40 continues to decrease. However, if the thickness of the gate poly oxide layer 40 is too small, the characteristics of the gate poly oxide layer may be degraded, the semiconductor substrate 10 may be damaged, pitting of the substrate may occur, and junction leakage current may increase.
As shown in FIG. 3, a middle temperature oxide (MTO) layer 50 and a spacer layer 60 are sequentially deposited on the gate poly oxide layer 40. The MTO layer 50 is introduced for obtaining etching margins required in forming gate spacers. As the thickness of the MTO layer 50 increases, a greater etching margin is ensured. However, since the size of a MOS transistor increases in accordance with an increase in the thickness of the MTO layer 50, there is a limit to how thick the MTO layer 50 can be. Next, the spacer layer 60, the MTO layer 50, and the gate poly oxide layer 40 are anisotropically etched, thereby forming gate spacers.
However, as shown in FIG. 4, in a MOS transistor formed through such a method, pitting 70 occurs on the surface of the semiconductor substrate 10. This is because the gate poly oxide layer 40 and the MTO layer 50 are formed too thin due to the decrease in the size of the MOS transistor and thus the gate poly oxide layer 40 and the MTO layer 50 cannot perform their functions well. In particular, since the gate poly oxide layer 40 directly contacting the semiconductor substrate 10 is thinly formed, it is difficult to maintain a sufficient etching selection ratio of the gate poly oxide layer 40 with respect to the spacer layer 60 during the anisotropic etching for forming the gate spacers, and thus the semiconductor substrate 10 is prone to be damaged by the anisotropic etching. As a result, pitting 70 occurs on the surface of the semiconductor substrate 10 so that an increase in junction leakage current may be caused and a whole device may be defective.
To solve the above-described problems, it is a first object of the present invention to provide a method for forming a MOS transistor which is capable of preventing damage to a semiconductor substrate and junction leakage current caused by etching to form spacers.
It is a second object of the present invention to provide a MOS transistor formed through such a method.
According to a first aspect of the invention, there is provided a method for forming a MOS transistor. A gate oxide layer pattern and a gate conductive layer pattern are formed on a semiconductor substrate. A mask layer pattern is formed on the semiconductor substrate and the gate conductive layer pattern so that the gate conductive layer pattern is completely covered with the mask layer pattern. The semiconductor substrate is made to be amorphous using the mask layer pattern. The mask layer pattern is removed, and a gate poly oxide layer is deposited over the entire surface of the semiconductor substrate. A gate spacer layer is deposited on the gate poly oxide layer and gate spacers are formed by anisotropically etching the gate spacer layer and the gate poly oxide layer. A source/drain region is formed on the semiconductor substrate.
Preferably, the sidewall of the gate conductive layer pattern is isolated from the sidewall of the mask layer pattern by 60-140 xc3x85.
Preferably, the step of making the semiconductor substrate amorphous is performed by implanting Si or Ge ions into portions of the semiconductor substrate using the mask layer pattern as an ion implantation mask.
Preferably, the gate poly oxide layer is grown to have different thicknesses including a first thickness and a second thickness. The second thickness is greater than the first thickness. Preferably, the gate poly oxide layer formed to have the second thickness is positioned on only the portions of the semiconductor substrate that have been made to be amorphous.
Preferably, the first thickness of the gate poly oxide layer is 10-50 xc3x85.
Preferably, the second thickness of the gate poly oxide layer is six times greater than the first thickness of the gate poly oxide layer.
Preferably, a middle temperature oxide (MTO) layer is further formed on the gate poly oxide layer after depositing the gate poly oxide layer over the entire surface of the semiconductor substrate.
In accordance with another aspect of the invention, there is provided another method for forming a MOS transistor. A gate oxide layer pattern and a gate conductive layer pattern are formed on a semiconductor substrate. A mask layer pattern is formed to have a size larger than the gate conductive layer pattern on the gate conductive layer pattern. The semiconductor substrate is made to be amorphous using the mask layer pattern. The mask layer pattern is removed, and a gate poly oxide layer is deposited over the entire surface of the semiconductor substrate. A gate spacer layer is deposited on the gate poly oxide layer and gate spacers are formed by anisotropically etching the gate spacer layer and the gate poly oxide layer. A source/drain region is formed on the semiconductor substrate.
Preferably, the step of forming the mask layer pattern includes forming an anti-reflection coating (ARC) layer on the gate conductive layer pattern, and patterning the gate oxide layer pattern and the gate conductive layer pattern by skew-etching so that the gate oxide layer pattern and the gate conductive layer pattern have a size smaller than the top surface of the ARC layer pattern.
Preferably, the step of making the semiconductor substrate amorphous is performed by implanting Si or Ge ions into portions of the semiconductor substrate using the mask layer pattern as an ion implantation mask.
Preferably, the gate poly oxide layer is grown to have different thicknesses including a first thickness and a second thickness. The second thickness is greater than the first thickness.
Preferably, a middle temperature oxide (MTO) layer is further formed on the gate poly oxide layer after the step of removing the mask layer pattern and depositing the gate poly oxide layer.
In accordance with another aspect of the invention, there is provided a MOS transistor. The transistor includes a gate oxide layer pattern and a gate conductive layer pattern formed on a semiconductor substrate, a gate spacer layer formed at the sidewalls of the gate conductive layer pattern. A gate poly oxide layer is formed to have different thicknesses including a first thickness and a second thickness between the semiconductor substrate and the bottom of the gate spacer layer. A source/drain region is formed on the semiconductor substrate.
Preferably, the second thickness is the thickness of the gate poly oxide layer at the sidewall of the gate spacer layer. Preferably, the second thickness of the gate poly oxide layer is greater than the first thickness of the gate poly oxide layer.
According to the present invention, it is possible to thickly form a gate poly oxide layer on a semiconductor substrate that is made to be amorphous by making exposed portions of the semiconductor substrate amorphous during a process of etching gate spacers. Accordingly, it is possible to prevent damage to the semiconductor substrate, such as pitting of the semiconductor substrate, and reduce an increase in junction leakage introduced by the occurrence of pitting. In addition, it is possible to thinly form a junction region by implantation of ions having a low energy, and thus the performance of a MOS transistor can be improved.